Apparatus for merging a plurality of data streams into a single data stream

ABSTRACT

An I/O device that includes: an input port; an input buffer coupled to the input port; an internal port operable to store packets generated by the I/O device; an internal buffer coupled to the internal port; a plurality of packet ID arrival registers coupled to the input port and the internal port; autocorrelation logic coupled to the plurality of packet ID arrival registers; an arbiter coupled to the autocorrelation logic; a packet selector coupled to the arbiter, the input buffer and the internal buffer; and an output port coupled to the packet selector.

[0001] This patent application discloses subject matter that is relatedto the subject matter disclosed in U.S. patent application Ser. No.______ entitled “Method for Merging a Plurality of Data Streams into aSingle Data Stream” filed on even date herein. The above PatentApplication is hereby incorporated by reference.

1. FIELD OF THE INVENTION

[0002] The present invention generally relates to I/O devices. Morespecifically, the present invention relates to a novel apparatus thatmerges a plurality of data streams into a single data stream.

2. BACKGROUND

[0003] In an effort to increase I/O bandwidth in high performanceprocessor based systems, a number of companies have developed theHyperTransport (“HT”) I/O interconnect structure. Briefly, the HT I/Obus structure is a scalable device level architecture that provides asignificant increase in transaction throughput over existing I/O busarchitectures such as Peripheral Component Interconnect (“PCI”) andAdvanced Graphics Port (“AGP”).

[0004] The foundation of the HT I/O bus is dual point-to-pointunidirectional links consisting of a data path, control signals, andclock signals. The HT I/O bus can provide both point-to-point links anda scalable network topology using HT I/O switching fabrics. Thus, an HTbased system can be expanded using HT switches to support multilevel,highly complex systems.

[0005] Communications between multiple HT I/O devices are known as datastreams. Each data stream contains one or more packets of information.Each packet of information contains a packet ID and a data payload. Thepacket ID is also commonly referred to as a unit ID. Because all packetsare transferred to or from a host bridge, the packet ID providesinformation that can be utilized to determine the source or destinationof the packet. A more detailed description of the HT I/O bus structureis presented in Appendix A.

[0006]FIG. 1 presents an HT I/O device 100 that interfaces with a firstunidirectional link 110 and a second unidirectional link 120. Thus, theHT I/O device 100 can receive input data streams and transmit outputdata streams via unidirectional links 110 and 120. The HT I/O device 100contains input ports 130 and 150 for receiving data streams and outputports 140 and 160 for transmitting data streams. The HT device 100 mayalso contain circuitry for generating packets that can be transmitted asoutput data streams via the output ports 140 and 160.

[0007] HT I/O devices may also be daisy chained as shown in FIG. 2. FIG.2 presents a portion of a single unidirectional link in an HT I/O bus.The unidirectional link shown contains three HT I/O devices 210, 220,and 230. If the first HT I/O device 210 receives a data stream with adestination ID that is equal to the ID of the first HT I/O device 210,then the first HT I/O device 210 will receive and internally process thedata stream. However, if the destination ID is not equal to the ID ofthe first HT I/O device 210, then the first HT I/O device 210 willforward the data stream to the second HT I/O device 220.

[0008] As the first HT I/O device 210 may also have the capability togenerate packets, the output data stream of the first HT I/O device 210is a composite of the input packet stream received by the first HT I/Odevice 210 and the internally generated packets. These internallygenerated packets will be referred to as an internal data stream.

[0009] The data stream received by the first HT I/O device 210 and thedevice's internal data stream may vary with time. For example, the inputdata stream for the first HT I/O device 210 may contain no packets overa given time interval. Thus, all packets in the internal data streamgenerated during that time interval by the first HT I/O device 210 maybe transmitted through the first HT I/O device's output port.Alternately, if the data stream received by the first HT I/O device 210and the device's internal data stream both contain a large number ofpackets, the HT I/O device may be required to choose between forwardingthe received data stream or outputting the internally generated packets.The process by which such a choice is made is known in the art as aforwarding fairness algorithm.

[0010] Prior art systems allow an HT I/O device to insert internallygenerated packets into an output data stream freely if the output datastream is empty. However, if the output data stream contains a largenumber of packets, the prior art systems only allow the HT I/O device toinsert internally generated packets into the output data stream at arate that is not greater than the rate that the HT I/O device isreceiving and forwarding packets from another HT I/O device. Such priorart systems are not optimal. Thus, a more optimal apparatus for mergingtwo data streams into a single data stream is needed.

3. SUMMARY OF INVENTION

[0011] One embodiment of the invention is an I/O device that includes:an input port; an input buffer coupled to the input port; an internalport operable to store packets generated by the I/O device; an internalbuffer coupled to the internal port; a plurality of packet ID arrivalregisters coupled to the input port and the internal port;autocorrelation logic coupled to the plurality of packet ID arrivalregisters; an arbiter coupled to the autocorrelation logic; a packetselector coupled to the arbiter, the input buffer and the internalbuffer; and an output port coupled to the packet selector.

[0012] In another embodiment of the invention, the arbiter includes anautocorrelation magnitude table.

[0013] In another embodiment of the invention, the arbiter includes amaximum autocorrelation magnitude table.

[0014] In another embodiment of the invention, the arbiter is operableto command the packet selector to select a packet from one of theplurality of input buffers based upon the output of the autocorrelationlogic.

[0015] Another embodiment of the invention is an I/O device thatincludes: a first input port; a first input buffer coupled to the firstinput port; a second input port; a second input buffer coupled to thesecond input port; a plurality of packet ID arrival registers coupled tothe first input port and the second input port; autocorrelation logiccoupled to the plurality of packet ID arrival registers; an arbitercoupled to the autocorrelation logic; a packet selector coupled to thearbiter, the first input buffer and the second input buffer; and anoutput port coupled to the packet selector.

[0016] Another embodiment of the invention is an I/O device thatincludes: a first internal port operable to store packets generated bythe I/O device; a first internal buffer coupled to the first internalport; a second internal port operable to store packets generated by theI/O device; a second internal buffer coupled to the second internalport; a plurality of packet ID arrival registers coupled to the firstinternal port and the second internal port; autocorrelation logiccoupled to the plurality of packet ID arrival registers; an arbitercoupled to the autocorrelation logic; a packet selector coupled to thearbiter, the first internal buffer and the second internal buffer; andan output port coupled to the packet selector.

[0017] Another embodiment of the invention is an HT I/O device thatincludes: an input port; an input buffer coupled to the input port; aninternal port for storing packets generated by the HT I/O device; aninternal buffer coupled to the internal port; and a plurality of packetID arrival registers coupled to the input port and the internal port.

4. BRIEF DESCRIPTION OF THE FIGURES

[0018]FIG. 1 presents an HT I/O device that interfaces with twounidirectional links.

[0019]FIG. 2 presents a portion of a single unidirectional link in an HTI/O bus.

[0020]FIG. 3 presents a portion of an HT I/O device.

[0021]FIG. 4 presents one embodiment of an input port.

[0022]FIG. 5 presents one embodiment of an output port.

[0023]FIG. 6 presents one method of utilizing data contained in a packetID arrival register in an autocorrelation function.

[0024]FIG. 7 presents one embodiment of an autocorrelation magnitudetable and one embodiment of a maximum autocorrelation magnitude table.

[0025]FIG. 8 presents a portion of an HT I/O switch.

[0026]FIG. 9 presents a portion of an HT I/O device with two internalports.

[0027]FIG. 10 presents a portion of an HT I/O device that sends flowcontrol information to packet transmitters.

[0028]FIG. 11 presents a flow chart of a method to store data in aplurality of registers.

[0029]FIG. 12 presents a flow chart of a method to merge two datastreams to generate a third data stream.

5. DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0030] The following description is presented to enable any personskilled in the art to make and use the invention, and is provided in thecontext of a particular application and its requirements. Variousmodifications to the disclosed embodiments will be readily apparent tothose skilled in the art, and the general principles defined herein maybe applied to other embodiments and applications without departing fromthe spirit and scope of the present invention. Thus, the presentinvention is not intended to be limited to the embodiments shown, but isto be accorded the widest scope consistent with the principles andfeatures disclosed herein.

[0031]FIG. 3 presents a portion of an HT I/O device 300. The HT I/Odevice 300 is coupled to a unidirectional link in an HT I/O busstructure. The HT I/O device 300 would also typically be coupled toanother unidirectional link. However, this second unidirectional link isnot shown in order not to obscure the invention.

[0032] 5.1 Input Port

[0033] The HT I/O device 300 can receive a data stream via the device'sinput port 310. The input port 310 may be any type of port that isoperable to receive a data stream. In one embodiment, the input port 310includes a plurality of input receivers configured as shown in FIG. 4.Each of the plurality of input receivers can receive a singledifferential signal. Examples of such differential signals could includecommand, address, data, clock, and control signals. By includingsufficient input receivers configured as shown in FIG. 4, the HT I/Odevice 300 can receive a data stream from an HT I/O bus.

[0034] 5.2 Internal Port

[0035] In addition to the input port 310, the HT I/O device may includean internal port 320. The internal port 320 may be any type of port thatis operable to receive and optionally temporarily store, one or morepackets in a data stream that were generated by the HT I/O device 300.For example, the internal port 320 may be a buffer such as a circularbuffer, a first-in-first-out buffer, or a queue buffer. Alternatively,the internal port 320 may be one or more registers.

[0036] 5.3 Input Buffers

[0037] As shown in FIG. 3, the input port 310 is coupled to a pluralityof input buffers 330. Input buffers 331, 332, and 333 may be any type ofbuffer, such as but not limited to circular buffers, first-in-first-outbuffers, or queue buffers. Alternatively, such buffers may be aplurality of registers. Each of the input buffers 331, 332, and 333 isassociated with a unique ID. As shown in FIG. 3, the first input buffer331 is associated with ID 0, the second input buffer 332 is associatedwith ID 1, and the third input buffer 333 is associated with ID m. Theseinput buffers 331, 332, and 333 store packets having a packet ID that isequal to the ID associated with the input buffer.

[0038] For example, ID 0 may be set to 10h. Thus, if two packets arereceived by input port 310 and the packet ID for both of the packets isequal to 10h, then the packets would be stored in the first input buffer331. Because the ID of each input buffer is unique, the packets wouldonly be stored in a single input buffer.

[0039] 5.4 Internal Buffers

[0040] In embodiments of the invention that include an internal port320, the internal port 320 may be coupled to a single internal buffer(not shown) or a plurality of internal buffers 340. Internal buffers 341and 342 may be any type of buffer or register. Each of the internalbuffers 341 and 342 is associated with a unique ID. As shown in FIG. 3,the first internal buffer 341 is associated with ID p and the secondinput buffer 342 is associated with ID q. These internal buffers 341 and342 store packets generated internally by the HT I/O device having apacket ID that is equal to the ID associated with the internal buffer.

[0041] A summary of the previously discussed method of storing packetsin input buffers 330 and/or in internal buffers 340 is summarized inFIG. 10.

[0042] 5.5 Packet ID Arrival Registers

[0043] As shown in FIG. 3, the input port 310 is also coupled to aplurality of packet ID arrival registers 350. Each of these registers isassociated with a unique ID. As shown in FIG. 3, the first packet IDarrival register 351 is associated with ID 0, the second packet IDarrival register 352 is associated with ID 1, and the third packet IDarrival register 353 is associated with ID m. These packet ID arrivalregisters 351, 352, and 353 store data that indicates whether a packetreceived by the input port 310 contains a packet ID that is equal to theID associated with the packet ID arrival register.

[0044] For example, as discussed above, ID 0 may be set to 10h. Thus, ifa packet is received by input port 310 and the packet ID is equal to10h, then data, such as a “1” would be stored in the first packet IDarrival register 351. Because the ID of each packet ID arrival registeris unique, data, such as a “0”, would be stored in each of the otherpacket ID arrival registers.

[0045] A packet ID arrival register may be any type of register.However, in some embodiments of the invention, the packet ID arrivalregisters would be shift registers so that older data could beefficiently shifted out as new data is stored in the packet ID arrivalregisters.

[0046] In embodiments of the invention that include an internal port320, the internal port 320 is also coupled to the plurality of packet IDarrival registers 350. In these embodiments, a packet ID arrivalregister's ID, such as the fourth packet ID arrival register's ID, ID p,shown in FIG. 3, may be set to 15h. Thus, if the HT I/O device 300internally generates a packet with a packet ID equal to 15h, and thepacket is sent to the internal port, then data, such as a “1”, would bestored in the fourth packet ID arrival register 354. Because the ID ofeach packet ID arrival register is unique, data, such as a “0”, would bestored in each of the other packet ID arrival registers 351, 352, 353and 355.

[0047] 5.6 Autocorrelation Logic

[0048] The packet ID arrival registers are coupled to autocorrelationlogic 360. In one embodiment, for each packet ID arrival register, theautocorrelation logic 360 uses the data stored in the packet ID arrivalregister to calculate the autocorrelation vector, Rxx(T), of the datastored in the packet ID arrival register over the interval T. Theautocorrelation vector of such data can be calculated using thefollowing equation:${{Rxx}(T)} = {{\frac{1}{N - T}{\sum\limits_{n = 0}^{N - 1}\quad {{x(n)}{x\left( {n + T} \right)}\quad T}}} = \left( {0,1,2,\ldots \quad,{N - 1}} \right)}$

[0049] In the above equation, T and N are integers, and x( ) is an arraythat includes data stored in one of the plurality of packet ID arrivalregisters 350. Conceptually, the summed portion of the above equationcorresponds to taking data in a packet ID arrival register, shifting itby T elements, multiplying the result element by element with theunshifted packet ID arrival register, and then summing the products.Thus, the magnitude of the autocorrelation vector, Rxx(T), representsthe approximate arrival rate of incoming packets. Similarly, peaks inthe autocorrelation vector, Rxx(T), approximate the average arrivalfrequency of incoming packets.

[0050]FIG. 6 indicates how the data contained in the first packet IDarrival register 351 can be utilized in the above equation. The rightmost element in the first packet ID arrival register 351 is addressed asx(0). Similarly, the leftmost element in the first packet ID arrivalregister 351 is addressed as x(5). As discussed above, a “1” in thearray indicates the arrival of a packet that contains a packet ID thatis equal to the ID associated with a specific packet ID arrivalregister. Similarly, a “0” in the array indicates the arrival of apacket that contains a packet ID that is not equal to the ID of aspecific packet ID arrival register. By selecting such values for thearray, i.e., “1” and “0”, the multiplication product x(n)x(n+1) may bereplaced with x(n) & x(n+T). Such a replacement will reduce thecomplexity and die size of the autocorrelation logic 360.

[0051] In other embodiments of the invention, the above autocorrelationvector, Rxx(T), is scaled. For example, the biased estimate of theautocorrelation vector: ${{Rxx}_{biased}(T)} = \frac{{Rxx}(T)}{N - 1}$

[0052] may be calculated by the autocorrelation logic 360.Alternatively, the unbiased estimate of the autocorrelation vector:${{Rxx}_{unbiased}(T)} = \frac{{Rxx}(T)}{N - 1 - {T}}$

[0053] may be calculated by the autocorrelation logic 360.

[0054] 5.7 Arbiter

[0055] The packet arrival determination logic 360 is coupled to anarbiter 370 as shown in FIG. 3. The arbiter 370 receives theautocorrelation vectors from the packet arrival determination logic 360and determines which packet should be output by the output port 329.

[0056] In one embodiment, the arbiter 370 contains an autocorrelationmagnitude table 700. As shown in FIG. 7, each row of the autocorrelationmagnitude table 700 is associated with a packet ID arrival register. Inaddition, each column in the autocorrelation magnitude table 700 isassociated with a packet whose arrival data is stored in a packet IDarrival register. The autocorrelation magnitude table 700 may be abuffer such as a circular buffer, a first-in-first-out buffer, or aqueue buffer. Alternatively, the autocorrelation magnitude table 700 maybe composed of registers such as shift registers.

[0057] In addition to the autocorrelation magnitude table 700, thearbiter may also contain a maximum autocorrelation magnitude table 710.Each element of the maximum autocorrelation magnitude table 710 isassociated with a row of the autocorrelation magnitude table 700, andhence, a packet ID arrival register and a packet ID. The maximumautocorrelation magnitude table 710 may be composed of any of the abovebuffers or registers.

[0058] After the arbiter 370 receives the autocorrelation vector,Rxx(T), for each of the plurality of packet ID arrival registers 350,the arbiter 370 calculates the magnitude of each of the autocorrelationvectors and stores the magnitudes in the autocorrelation magnitude table700.

[0059] Next, for each row in the maximum autocorrelation magnitude table710, the arbiter 370 calculates the maximum of the autocorrelationmagnitudes in each row of the autocorrelation magnitude table 700 andplaces such maximum values in the maximum autocorrelation magnitudetable 710. For example, if the maximum autocorrelation magnitude of the6 elements in the autocorrelation magnitude table row associated with ID0, as shown in FIG. 7, is 10h then the value of 10h would be stored inthe first row of the maximum autocorrelation magnitude table 710.

[0060] Next, the arbiter 370 determines which element in the maximumautocorrelation magnitude table 710 contains the largest autocorrelationmagnitude. The arbiter 370 then issues a command to the packet selector380, which is discussed in Section 5.8, to select a packet with thepacket ID that is associated with such element.

[0061] In still other embodiments of the invention, the arbiter 370receives Rxx_(biased)(T) or Rxx_(unbiased)(T) vectors instead of theRxx(T) vectors discussed above. In these embodiments, the arbitrationmethods would be substantially identical to the methods discussed above.

[0062] 5.8 Packet Selector

[0063] The input buffers 330, the internal buffers 340, and the arbiter370 are each coupled to a packet selector 380. The packet selector 380can receive packets from any of the plurality of input buffers 330 orfrom any of the plurality of internal buffers 340. However, the packetselector 380 will receive a packet from these buffers 330 and 340 whenit is commanded to do so by the arbiter 370. Thus, when the packetselector 380 receives a command from the arbiter 370 to select a packetfrom one of these buffers 330 and 340, the packet selector 380 receivesa packet and passes the packet to the output port 390.

[0064] 5.9 Output Port

[0065] As shown in FIG. 3, the packet selector 380 is coupled to anoutput port 390. The output port may be any type of port that isoperable to generate a data stream. In one embodiment, the output portincludes a plurality of output drivers configured as shown in FIG. 5.Each of the plurality of output drivers can generate a singledifferential signal, such as but not limited to, command, address, data,clock, and control signals.

[0066] 5.10 Source IDs, Destination IDs, and Packet IDs

[0067] In the above description, packet IDs, which provide informationrelating to the source or destination of packets, were associated withspecific input buffers, internal buffers, and packet ID arrivalregisters. However, in other embodiments of the invention, the inputbuffers, internal buffers, and packet ID arrival registers could beassociated with any packet information that can be utilized to identifya packet.

[0068] 5.11 Data Streams

[0069] As discussed above, FIG. 3 presents only a portion of an HT I/Odevice 300. The HT I/O device 300 is shown coupled to a singleunidirectional link in an HT I/O bus structure. The HT I/O device 300would also typically be coupled to another unidirectional link. However,this second unidirectional link is not shown in order not to obscure theinvention. In many of the embodiments of the invention, the HT I/Odevice 300 would also include input buffers, internal buffers, packet IDarrival registers, autocorrelation logic, an arbiter, and a packetselector. These components would operate as discussed above to merge aninput data stream from the second unidirectional link with the HT I/Odevice's internal data stream into a single output data stream on thesecond unidirectional link.

[0070] While some of the embodiments discussed above merge an input datastream and an internal data stream into a single output data stream, theinvention is not so limited. Some embodiments of the invention merge adata stream from one input port with other data stream(s) from one ormore input ports. For example, FIG. 8 presents an HT I/O switch capableof merging data streams received from a plurality of input ports into asingle output data stream.

[0071] Other embodiments of the invention, such as shown in FIG. 9,would merge a plurality of internal data streams into a single outputdata stream. Still other embodiments of the invention would merge one ormore input data streams with one or more internal data streams.

[0072] 5.12 Buffer Credits

[0073] Some bus architectures, such as the HT I/O bus architecture, areflow controlled using a coupon-based scheme. In such bus architectures,a packet transmitter contains a counter that corresponds to the freespace available in a buffer at the packet receiver, such as an HT I/Odevice. After initialization, the packet receiver sends packets to thepacket transmitter to indicate the free space available in the packettransmitter buffer. This information is stored in a counter in thepacket transmitter. Thereafter, when the packet transmitter sends apacket to the packet receiver, the packet transmitter decrements thecounter. If the counter ever reaches zero, the packet transmitter ceasessending packets to the packet receiver.

[0074] In some embodiments of the invention, such as shown in FIG. 10,when the HT device 900 passes a packet to the first output port 990, theHT device also sends a packet containing flow control information to thepacket transmitter via the second output port 995.

[0075] 5.13 Conclusion

[0076] A summary of the previously discussed method of merging a firstdata stream with a second data stream to generate a third data stream issummarized in FIG. 12.

[0077] The foregoing descriptions of embodiments of the presentinvention have been presented for purposes of illustration anddescription only. They are not intended to be exhaustive or to limit thepresent invention to the forms disclosed. Accordingly, manymodifications and variations will be apparent to practitioners skilledin the art. Additionally, the above disclosure is not intended to limitthe present invention. The scope of the present invention is defined bythe appended claims.

I claim:
 1. An I/O device comprising: a) an input port; b) an inputbuffer coupled to the input port; c) an internal port operable to storepackets generated by the I/O device; d) an internal buffer coupled tothe internal port; e) a plurality of packet ID arrival registers coupledto the input port and the internal port; f) autocorrelation logiccoupled to the plurality of packet ID arrival registers; g) an arbitercoupled to the autocorrelation logic; h) a packet selector coupled tothe arbiter, the input buffer and the internal buffer; and i) an outputport coupled to the packet selector.
 2. The I/O device of claim 1wherein the I/O device is a HyperTransport I/O device.
 3. The I/O deviceof claim 1, wherein the input port is coupled to a HyperTransport I/Odevice by a link.
 4. The I/O device of claim 1, wherein the input buffercontains a packet containing a packet ID and a data payload, and whereinone of the plurality of the packet ID arrival registers contains datathat indicates that the packet ID is equal to the ID associated with thepacket ID arrival register.
 5. The I/O device of claim 1, wherein theinput buffer contains a packet containing a packet ID and a datapayload, and wherein one of the plurality of the packet ID arrivalregisters contains data that indicates that the packet ID is not equalto the ID associated with the packet ID arrival register.
 6. The I/Odevice of claim 1, wherein the autocorrelation logic is operable tocalculate an autocorrelation vector of a plurality of packets having afirst packet ID.
 7. The I/O device of claim 1, wherein the arbiterincludes an autocorrelation magnitude table.
 8. The I/O device of claim1, wherein the arbiter includes a maximum autocorrelation magnitudetable.
 9. The I/O device of claim 1, wherein the arbiter is operable tocommand the packet selector to select a packet from one of the pluralityof input buffers based upon the output of the autocorrelation logic. 10.The I/O device of claim 1, wherein the arbiter contains circuitry forcommanding the packet selector to select a packet from either the firstinput buffer or the second input buffer based upon the output of theautocorrelation logic.
 11. The I/O device of claim 1, wherein the outputport is coupled to a HyperTransport I/O device by a link.
 12. An I/Odevice comprising: a) a first input port; b) a first input buffercoupled to the first input port; c) a second input port; d) a secondinput buffer coupled to the second input port; e) a plurality of packetID arrival registers coupled to the first input port and the secondinput port; f) autocorrelation logic coupled to the plurality of packetID arrival registers; g) an arbiter coupled to the autocorrelationlogic; h) a packet selector coupled to the arbiter, the first inputbuffer and the second input buffer; and i) an output port coupled to thepacket selector.
 13. The I/O device of claim 12 wherein the I/O deviceis a HyperTransport I/O device.
 14. The I/O device of claim 12, whereinthe first input port is coupled to a first HyperTransport I/O device bya first link and the second input port ID is coupled to a secondHyperTransport I/O device by a second link.
 15. The I/O device of claim12, wherein the first input buffer contains a packet with a packet IDand a data payload, and wherein one of the plurality of packet IDarrival registers contains data that indicates that the packet ID isequal to the ID associated with the packet ID arrival register.
 16. TheI/O device of claim 12, wherein the first input buffer contains a packetwith a packet ID and a data payload, and wherein one of the plurality ofpacket ID arrival registers contains data that indicates that the packetID is not equal to the ID associated with the packet ID arrivalregister.
 17. The I/O device of claim 12, wherein the autocorrelationlogic is operable to calculate an autocorrelation vector of a pluralityof packets having a first packet ID.
 18. The I/O device of claim 12,wherein the arbiter includes an autocorrelation magnitude table.
 19. TheI/O device of claim 12, wherein the arbiter includes a maximumautocorrelation magnitude table.
 20. The I/O device of claim 12, whereinthe arbiter is operable to command the packet selector to select apacket from one of the plurality of input buffers based upon the outputof the autocorrelation logic.
 21. The I/O device of claim 12, whereinthe arbiter contains circuitry for commanding the packet selector toselect a packet from either the first input buffer or the second inputbuffer based upon the output of the autocorrelation logic.
 22. The I/Odevice of claim 12, wherein the output port is coupled to aHyperTransport I/O device by a link.
 23. An I/O device comprising: a) afirst internal port operable to store packets generated by the I/Odevice; b) a first internal buffer coupled to the first internal port;c) a second internal port operable to store packets generated by the I/Odevice; d) a second internal buffer coupled to the second internal port;e) a plurality of packet ID arrival registers coupled to the firstinternal port and the second internal port; f) autocorrelation logiccoupled to the plurality of packet ID arrival registers; g) an arbitercoupled to the autocorrelation logic; h) a packet selector coupled tothe arbiter, the first internal buffer and the second internal buffer;and i) an output port coupled to the packet selector.
 24. The I/O deviceof claim 24 wherein the I/O device is a HyperTransport I/O device. 25.The I/O device of claim 23, wherein the first internal port is coupledto a first HyperTransport I/O device by a first link and the secondinternal port ID is coupled to a second HyperTransport I/O device by asecond link.
 26. The I/O device of claim 23, wherein the first internalbuffer contains a packet with a packet ID and a data payload, andwherein one of the plurality of packet ID arrival registers containsdata that indicates that the packet ID is equal to the ID associatedwith the packet ID arrival register.
 27. The I/O device of claim 23,wherein the first internal buffer contains a packet with a packet ID anda data payload, and wherein one of the plurality of packet ID arrivalregisters contains data that indicates that the packet ID is not equalto the ID associated with the packet ID arrival register.
 28. The I/Odevice of claim 23, wherein the autocorrelation logic is operable tocalculate an autocorrelation vector of a plurality of packets having afirst packet ID.
 29. The I/O device of claim 23, wherein the arbiterincludes an autocorrelation magnitude table.
 30. The I/O device of claim23, wherein the arbiter includes a maximum autocorrelation magnitudetable.
 31. The I/O device of claim 23, wherein the arbiter is operableto command the packet selector to select a packet from one of theplurality of internal buffers based upon the output of theautocorrelation logic.
 32. The I/O device of claim 23, wherein thearbiter contains circuitry for commanding the packet selector to selecta packet from either the first internal buffer or the second internalbuffer based upon the output of the autocorrelation logic.
 33. The I/Odevice of claim 23, wherein the output port is coupled to aHyperTransport I/O device by a link.
 34. An HT I/O device comprising: a)an input port; b) an input buffer coupled to the input port; c) aninternal port for storing packets generated by the HT I/O device; d) aninternal buffer coupled to the internal port; and e) a plurality ofpacket ID arrival registers coupled to the input port and the internalport.
 35. The I/O device of claim 34, wherein the first internal buffercontains a packet with a packet ID and a data payload, and wherein oneof the plurality of packet ID arrival registers contains data thatindicates that the packet ID is equal to the ID associated with thepacket ID arrival register.
 36. The I/O device of claim 34, wherein thefirst internal buffer contains a packet with a packet ID and a datapayload, and wherein one of the plurality of packet ID arrival registerscontains data that indicates that the packet ID is not equal to the IDassociated with the packet ID arrival register.